In memory systems and microelectronics in general, there is a desire for performance, power conservation and component compatibility. These issues are especially important where design advances (both in memory technology and computing technology) are occurring at very rapid pace by mobile applications, high-powered applications, etc. (e.g., PC""s, mobile systems, printers, RAID applications).
In recent years, the need for improved memory system speed/performance has driven the development of synchronous SRAM and synchronous dynamic random access memory (SDRAM). Even more recently, so-called double-data-rate (DDR) SDRAM memory modules have been proposed and developed. The DDR-SDRAM effectively doubles the data throughput at a given system clock speed. These types of advances are expected to continue with the introduction higher clock speed versions of DDR-SDRAM (e.g., 166 MHz clock speed or greater). Discussions of SDRAM and DDR-SDRAM can be found in JEDEC standards publications. Another reference covering the background of this technology is the book, xe2x80x9cHigh Performance Memories,xe2x80x9d by Betty Prince, published by Wiley and Sons, (1999).
A main feature of synchronous memory systems is the presence of a clock or clock buffer source in direct communication with the individual memory module(s) of the memory system. Aspects of such systems are disclosed in US Pat. Nos. 5,896,346; 6,043,694; and 6,081,862; the disclosures of which is incorporated herein by reference. Other aspects are discussed in U.S. patent application Ser. No. 09/240,647, filed Jan. 29,1999, now U.S. Pat. No. 5,347,367, the disclosure of which is incorporated herein by reference.
DDR memory modules, such as 184 Pin DIMMs (dual-in-line memory modules) and 200 Pin SO DIMMs, currently include a differential clock termination scheme which is proving to be non-optimal in low power and low pin count (controller) applications. In addition, the emergence of improved clock drivers and broad adoption of registered DIMMs (with onboard clock regeneration) have created new system clocking opportunities that could improve overall system timing budgets if alternate module/system clock termination solutions were permitted. Unfortunately, the need for backward compatibility between emerging memory modules and current designs limit the ability of producers to develop new/unique modules that service these new opportunities, unless some means of maintaining backward compatibility is maintained.
Thus, there is a need for a way of maintaining compatibility between memory modules in the same memory system, and in particular, for memory systems containing both SDRAM DIMMs and DDR-SDRAM DIMMs. There is also an need for designs/methods of improving clock signal management flexibility.
The invention encompasses memory systems and/or memory modules which allow selectable clock termination between the clock/clock buffer and the memory modules. The invention provides a fully forward and backward compatible memory solution. The invention provides the memory modules themselves, and the systems that include enable/disable pin(s) to use these modules.
In one aspect the invention encompasses a memory assembly with a selectable termination of the system-level clock. The selectable clock termination may be located at any desired point(s) in the clock net (e.g., at or near an end of a clock net, a split point of a clock net, etc.). The selectability is preferably provided by one or more switches for enabling and/or disabling the clock termination. The switch(es) is preferably a FET switch connected to a pin on the memory assembly. The memory assembly preferably permits operation in systems having both single drop end-terminated clock nets and systems having multi-drop clock nets wherein clock termination method is preferably selected from the group consisting of (i) single end termination, (ii) source series termination, and (iii) source capacitive termination.
The invention also encompasses memory systems, especially synchronous memory systems capable of utilizing memory assemblies having selectable clock termination.
The invention also encompasses a memory controller that includes detection circuitry to determine the type of memory clock termination utilized, whereby the clock drive is adjusted to match the termination method. The invention further encompasses a memory system that includes such memory controller in combination with a memory assembly with a selectable system-level clock termination.
The invention further encompasses a memory module that includes more than one clock termination method, whereby the clock termination permits a multitude of memory assemblies to share a common clock pair or to operate with unique clock pairs to each memory assembly. The clock termination method is preferably selectable via a control signal (e.g., Vdd, VddQ or ground pin on the memory assembly) to the memory assembly. The memory module is preferably a DDR memory module, more preferably a 168-200 pin DIMM.
The invention also encompasses a memory subsystem that includes more than one clock termination method, whereby the clock termination permits a multitude of memory assemblies to share a common clock pair or to operate with unique clock pairs to each memory assembly. Preferably, a FET switch is integrated into a clock net of the subsystem to enable or disable clock termination on the memory assembly. The memory subsystem preferably includes the ability to have one or more clocks disabled via a FET switch which is integrated into a clock path.